The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each new generation has smaller and more complex circuits than the previous generation. These advances, however, have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of integrated circuit evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component or line that can be created using a fabrication process) has decreased. This scaling-down process generally provides benefits by increasing production efficiency and lowering associated costs. During the scaling trend, it has been desirable to improve performance of field effect transistors (FETs). One method to improve FET performance is to enhance the carrier mobility within the channel region, which is the region between the source and the drain of the FET. Although existing approaches had initially addressed some performance concerns, with continued device down scaling, they have not been entirely satisfactory in all respects. Accordingly, there is a need for an improved fabrication process (and resulting device).